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| Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor FEATURES * 'Trench' technology * Very low on-state resistance * Fast switching * Logic level compatible g PSMN010-55D QUICK REFERENCE DATA SYMBOL d VDSS = 55 V ID = 75 A RDS(ON) 10.5 m (VGS = 10 V) RDS(ON) 12 m (VGS = 5 V) s GENERAL DESCRIPTION SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:* d.c. to d.c. converters * switched mode power supplies The PSMN010-55D is supplied in the SOT428 (Dpak) surface mounting package. PINNING PIN 1 2 3 tab gate drain1 source DESCRIPTION SOT428 (DPAK) tab 2 drain 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Continuous gate-source voltage Peak pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tj 150 C Tmb = 25 C; VGS = 5 V Tmb = 100 C; VGS = 5 V Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 55 55 15 20 752 57 240 125 175 UNIT V V V V A A A W C 1 It is not possible to make connection to pin 2 of the SOT428 package. 2 Continuous current rating limited by package. October 1999 1 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 74 A; tp = 100 s; Tj prior to avalanche = 25C; VDD 25 V; RGS = 50 ; VGS = 5 V MIN. - PSMN010-55D MAX. 264 75 UNIT mJ A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT428 package, pcb mounted, minimum footprint TYP. MAX. UNIT 50 1.2 K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A VGS = 4.5 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175C Gate source leakage current VGS = 10 V; VDS = 0 V Zero gate voltage drain VDS = 25 V; VGS = 0 V; current Tj = 175C Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 75 A; VDD = 44 V; VGS = 5 V MIN. 55 42 1 0.5 TYP. MAX. UNIT 1.5 7.4 8.6 9.1 0.02 0.05 55 13 28 19 114 250 216 3.5 7.5 3300 560 370 2 2.3 10.5 12 13 25 100 10 500 V V V V V m m m m nA A A nC nC nC ns ns ns ns nH nH pF pF pF IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss VDD = 30 V; RD = 1.2 ; VGS = 10 V; RG = 10 Resistive load Measured tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz October 1999 2 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 25 A; VGS = 0 V IF = 25 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V - PSMN010-55D TYP. MAX. UNIT 0.95 70 0.16 75 240 1.2 A A V ns C October 1999 3 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN010-55D Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 10 Transient thermal impedance, Zth j-mb (K/W) 1 0.2 0.1 0.1 0.05 0.02 0.01 D = 0.5 P D tp D = tp/T single pulse T 0.001 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Drain Current, ID (A) VGS = 10V 5V 3V 2.8 V Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 50 45 40 35 30 25 20 15 10 5 0 0 Tj = 25 C 2.6 V 2.4 V 2.2 V 2V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS) 1000 0.05 0.045 tp = 10 us 0.04 0.035 100 us 1 ms 0.03 0.025 Drain-Source On Resistance, RDS(on) (Ohms) 2.2 V 2.4 V 2.6 V Tj = 25 C 2.8 V 100 10 0.02 0.015 3V 5V VGS = 10V D.C. 10 ms 100 ms 0.01 0.005 0 1000 0 5 10 15 20 25 30 Drain Current, ID (A) 35 1 1 10 100 Drain-Source Voltage, VDS (V) 40 45 50 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID) October 1999 4 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN010-55D Drain current, ID (A) 50 45 40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 Gate-source voltage, VGS (V) Tj = 25 C VDS > ID X RDS(ON) 2.25 2 1.75 1.5 1.25 1 0.75 175 C Threshold Voltage, VGS(TO) (V) maximum typical minimum 0.5 0.25 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temperature, Tj (C) Fig.7. Typical transfer characteristics. ID = f(VGS) Transconductance, gfs (S) VDS > ID X RDS(ON) Tj = 25 C 175 C Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 1.0E-01 Drain current, ID (A) 1.0E-02 1.0E-03 minimum typical 1.0E-04 maximum 1.0E-05 1.0E-06 0 5 10 15 20 25 30 35 Drain current, ID (A) 40 45 50 0 0.5 1 1.5 2 Gate-source voltage, VGS (V) 2.5 3 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID) Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS Normalised On-state Resistance 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) 10000 Capacitances, Ciss, Coss, Crss (pF) Ciss 1000 Coss Crss 100 0.1 1 10 Drain-Source Voltage, VDS (V) 100 Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj) Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz October 1999 5 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor PSMN010-55D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Gate-source voltage, VGS (V) ID = 75 A Tj = 25 C 100 Maximum Avalanche Current, IAS (A) 25 C VDD = 11 V 10 Tj prior to avalanche = 150 C VDD = 44 V 0 10 20 30 40 50 60 70 Gate charge, QG (nC) 80 90 100 1 0.001 0.01 0.1 Avalanche time, tAV (ms) 1 10 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Source-Drain Diode Current, IF (A) 50 45 40 35 30 25 20 15 10 5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) 175 C Tj = 25 C VGS = 0 V Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj October 1999 6 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped) PSMN010-55D SOT428 seating plane y A E b2 A A1 mounting base A2 D1 E1 D HE L2 2 L L1 1 b1 e e1 b 3 wM A c 0 10 scale 20 mm DIMENSIONS (mm are the original dimensions) A UNIT max. mm 2.38 2.22 A1(1) 0.65 0.45 A2 0.89 0.71 b 0.89 0.71 b1 max. 1.1 0.9 b2 5.36 5.26 c 0.4 0.2 D1 E D max. max. max. 6.22 5.98 4.81 4.45 6.73 6.47 E1 min. 4.0 e e1 HE max. 10.4 9.6 L 2.95 2.55 L1 min. 0.5 L2 0.7 0.5 w 0.2 y max. 0.2 2.285 4.57 Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-04-07 Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". October 1999 7 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor MOUNTING INSTRUCTIONS Dimensions in mm 7.0 PSMN010-55D 7.0 2.15 2.5 1.5 4.57 Fig.17. SOT428 : soldering pattern for surface mounting. October 1999 8 Rev 1.200 Philips Semiconductors Product specification N-channel logic level TrenchMOSTM transistor DEFINITIONS Data sheet status Objective specification Product specification Limiting values PSMN010-55D This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. October 1999 9 Rev 1.200 |
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